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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:19:41 05/06/2011 
-- Design Name: 
-- Module Name:    Mult_Operation - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.Definitions.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mult_Operation is
    Port ( a : in  ext3;
           b : in  ext3;
           control : in  STD_LOGIC;
           salida : out  ext3);
end Mult_Operation;

architecture Behavioral of Mult_Operation is

begin

process(a, b, control) is
begin
	case control is
		when '0' => 
			salida <= a;
		when others =>
			salida <= b;
	end case;

end process;

end Behavioral;

